Referring to FIG. 1, during manufacture of an IC (integrated circuit) package 100, an IC die 102 is mounted onto a package substrate 104. For example, the IC package 100 may be a C4 IC package available from Advanced Micro Devices, Inc. having its principal place of business at Sunnyvale, Calif. Solder bumps 106A, 106B, and 106C are mounted to pads 108A, 108B, and 108C, respectively, for coupling nodes of the integrated circuit fabricated on the IC die 102 to leads (not shown in FIG. 1) of the package substrate 104. Such leads provide external access to the nodes of the integrated circuit fabricated on the IC die 102.
FIG. 2 shows a view of an upper surface 110 of the package substrate 104 having a plurality of circular pads 108A, 108B, 108C, 108D, 108E, 108F, 108G, 108H, and 108I exposed thereon. An area 112 (outlined in dashed lines in FIG. 2) of the package substrate 104 having such a plurality of pads therein is termed a “cage” of the package substrate 104. FIG. 1 illustrates a cross-sectional view of the package substrate 104 across line I—I in FIG. 2.
FIG. 3 shows a view of a bottom surface 114 of the IC die 102 having a plurality of solder bumps 106A, 106B, 106C, 106D, 106E, 106F, 106G, 106H, and 1061 formed thereon. FIG. 1 illustrates a cross-sectional view of the IC die 102 across line II—II in FIG. 3. Referring to FIGS. 1, 2, and 3, the IC die 102 is placed onto the package substrate 104 with the bottom surface 114 of the IC die 102 facing the top surface 110 of the package substrate 104.
The solder bumps 106A, 106B, 106C, 106D, 106E, 106F, 106G, 106H, and 106I of the IC die 102 are desired to be coupled to the pads 108A, 108B, 108C, 108D, 108E, 108F, 108G, 108H, and 108I, respectively, of the package substrate 104. Such solder bumps of the IC die 102 are coupled to such pads of the package substrate 104 via solder joints formed from the solder bumps in a reflow process, as known to one of ordinary skill in the art. An IC die and a package substrate typically have more numerous solder bumps and pads, respectively. However, nine solder bumps and nine pads are illustrated and described herein for the IC die 102 and package substrate 104 for simplicity and clarity of illustration.
For coupling with minimized resistance between the solder bumps of the IC die 102 and the pads of the package substrate 104, the respective center point of each of the solder bumps 106A, 106B, 106C, 106D, 106E, 106F, 106G, 106H, and 106I is desired to be aligned to the respective center point of each of the pads 108A, 108B, 108C, 108D, 108E, 108F, 108G, 108H, and 1081, respectively. Such alignment is illustrated with a dashed line 116 in FIG. 1 through the centers of the example solder bump 106B and the example corresponding pad 108B.
FIG. 4 illustrates the scenario when the IC die 102 is shifted undesirably too much to the left by a first misaligned displacement 118. Similarly, FIG. 5 illustrates the scenario when the IC die 102 is shifted undesirably too much to the right by a second misaligned displacement 120. Generally, the IC die 102 may be misaligned with respect to the package substrate 104 in any of a plurality of directions when the centers of the solder bumps of the IC die 102 are not aligned to the centers of the pads of the package substrate 104.
In any case of unacceptable misalignment, undesirably high resistances or even open circuits may result with such misaligned coupling between the solder bumps of the IC die 102 and the circular pads of the package substrate 104. In the example of FIGS. 2 and 3, each of the solder bumps 106A, 106B, 106C, 106D, 106E, 106F, 106G, 106H, and 106I of the IC die 102 and each of the circular pads 108A, 108B, 108C, 108D, 108E, 108F, 108G, 108H, and 108I of the package substrate 104 has a diameter 122 of about 100 μm (micrometers).
For proper operation of the IC package 100, each solder bump of the IC package 102 is desired to be aligned with a corresponding pad of the package substrate 104 with any misalignment being less than 10 μm (micrometers). Thus, a mechanism is desired for placing the IC die 102 onto the package substrate 104 with a desired level of alignment.
After placement of the IC die 102 onto the package substrate 104 with desired alignment, the IC die 102 is attached to the package substrate 104. Thereafter, a reflow process is performed for the IC die 102 and the package substrate 104 such that solder bumps of the IC die 102 become molten to be electrically connected to the pads of the package substrate 104. Such a reflow process is typically irreversible as known to one of ordinary skill in the art. On the other hand, even after the IC die 102 is attached to the package substrate 104, if the IC die 102 is deemed to be unacceptably misaligned to the package substrate 104, the IC die 102 may be removed from the package substrate 104 before the reflow process to be better aligned to the package substrate 104. Thus, a mechanism is desired for inspection of the alignment for the IC die attached to the package substrate before the reflow process.